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Capabilities

Architecture to silicon, under one roof.

Specification, RTL, verification, analog, physical design, DFT, and bring-up — seven disciplines that have to agree for a chip to actually work. One team owns all of them.

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Architecture

Specification and architecture

A spec is more than a feature list. We work the spec until block partitioning, process node, IP strategy, and tape-out plan all line up with budget and schedule.

  • Product spec and architecture document
  • Block partitioning and floorplan
  • Node and foundry selection
  • IP licensing strategy
  • Tape-out plan and budget
  • Risk register against first silicon

RTL design

Verilog and SystemVerilog

Clean, synthesisable RTL. Each block is built to be verified, not just to compile. Coding standards enforced from day one.

  • SystemVerilog RTL design
  • Reusable parameterised IP blocks
  • Clock domain crossing handling
  • Low-power and clock-gating discipline
  • Linting and CDC sign-off
  • Synthesis-aware coding

Verification

UVM, coverage-driven, sign-off clean

Constrained-random verification with UVM testbenches and explicit coverage goals. We close coverage before we close timing.

  • UVM testbench architecture
  • Functional and code coverage
  • Constrained-random stimulus
  • Assertion-based verification (SVA)
  • Formal property verification (selected blocks)
  • Regression infrastructure and triage

Analog & mixed-signal

Layout, simulation, integration

Where matching, noise, and parasitics dominate. Analog work that respects what the silicon can actually do.

  • Schematic capture and simulation
  • Analog and mixed-signal layout
  • Post-layout simulation (PEX, MC, corners)
  • AMS verification (Verilog-AMS)
  • ESD and latch-up review
  • Analog IP integration

Physical design

Floorplan to GDSII

Place-and-route, timing closure, IR drop, and physical sign-off for mature nodes from 180nm down to 28nm. No exotic node heroics.

  • Floorplan and power planning
  • Place-and-route
  • Multi-corner multi-mode STA
  • IR drop and EM analysis
  • DRC, LVS, ERC sign-off
  • Formal equivalence (LEC)

DFT

Design for test

Production test gets designed in, not bolted on. ATPG coverage targets agreed before RTL freeze.

  • Scan insertion and stitching
  • ATPG (stuck-at, transition)
  • MBIST for embedded memories
  • JTAG boundary scan
  • IEEE 1500 / IJTAG wrappers
  • Test program development

Tape-out & bring-up

Foundry, package, first silicon

GDSII through wafers, packaged parts, and characterised silicon ready to ship. Multi-project shuttle and full-reticle.

  • Tape-out coordination with foundry
  • OSAT package selection and qualification
  • Wafer probe and final test programs
  • Silicon bring-up and characterisation
  • Reference board and demo firmware
  • Production transfer to customer

EDA & tooling

The flows we actually use.

Licensed via startup and partner programs from the big three EDA vendors, plus the open tooling that lets us move fast on experiments.

Cadence

Virtuoso, Innovus, Genus, Xcelium

Synopsys

Design Compiler, VCS, IC Compiler II, PrimeTime

Siemens EDA

Questa, Calibre, Tessent

Verific

Parsers and linting platforms

GitHub / GitLab

Source control, CI, regression dashboards

Python / TCL

Flow automation and scripting

Nodes & foundries

Mature nodes, not heroics.

Mature digital

180 / 130 / 65 nm

Workhorse digital and mixed-signal — our default starting point.

Sub-100 advanced

40 / 28 nm

Where performance matters and the budget allows a tighter shuttle.

Analog / BCD

180 / 130 nm BCD

Power management, drivers, sensor front-ends.

FPGA prototyping

Xilinx / Intel

Early customer demos, software bring-up before tape-out.

Multi-project shuttle

Europractice, MOSIS, foundry direct

Low-cost first-silicon for prototypes and small volumes.

Foundries

TSMC, GF, UMC, Tower, SMIC

Selected per node, capacity, and IP availability.

Have a chip in mind?

Send a spec or a sketch. We will tell you what is feasible, what we'd change, and what it costs.

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